1. Field of the Invention
The present invention relates to a microcomputer including an electrically programmable erasable non-volatile memory. More specifically, the present invention relates to a microcomputer including a flash memory which allows modification/overwriting of a program stored therein in a simple manner.
2. Description of the Background Art
Recently, as personal computers have come to be widely used, various and many peripheral devices of the personal computers have also come to be used widely. Such personal devices include CD-ROM (Compact-Disk Read-Only Memory) drives, DVD-ROM (Digital Video Disk Read-Only Memory) drives and hard disk drives. These peripheral devices have characteristically short development cycles. Specifications are improved one after another and control programs are improved in a very short period of time, and therefore control programs of these devices are frequently revised. For this reason, a microcomputer including a flash memory allowing modification/overwriting of a program in a simple manner is advantageous, and hence used dominantly.
In a flash memory of such a microcomputer, a program and data including device parameters, country code and a program version number are stored. When a program is revised, or when it becomes necessary to adapt states of the device to the conditions and terms under which the device is to be used, the data are overwritten.
Referring to FIG. 1, a conventional microcomputer including a flash memory includes a flash memory 3 storing data such as program, connected to a data bus 7, an address bus 8 and read/write (RD/WR) signal line 9. The microcomputer further includes a CPU (Central Processing Unit) 1 connected to data bus 7, address bus 8 and RD/WR signal line 9 through a BIU (Bus Interface Unit) 2 for executing a program stored in flash memory 3, an external bus I/F (interface) circuit 15, an RAM (Random Access Memory) 4, peripheral devices such as a timer and a serial I/O (Input/Output), and an interrupt controlling circuit 14, which are all connected to data bus 7, address bus 8 and RD/WR signal line 9.
The microcomputer further includes an address predecoder 505 decoding an upper bit of an address applied through address bus 8 for selecting any of flash memory 3, RAM 4, peripheral device 13 and interrupt controlling circuit 14 and applying area signals ROMar, RAMar and SFRar (Special Function Register area), respectively.
Referring to FIG. 2, address predecoder 505 includes a predecoder 21 for the peripheral device 13, an RAM predecoder 22, and an ROM predecoder 23. Predecoder 21 for the peripheral device, RAM predecoder 22 and ROM predecoder 23 are all connected to address bus 8 for receiving and decoding an upper address and outputting the signals SFRar, RAMar and ROMar, respectively.
CPU 1 is capable of overwriting contents of flash memory 3. An operation mode of the microcomputer performing this process will be referred to as xe2x80x9cflash memory overwriting mode.xe2x80x9d
Generally, CPU 1 successively reads a program written in flash memory 3 and executes the program. In the flash memory overwriting mode, however, CPU 1 cannot read data written in flash memory 3. This is because the control voltages and the states of circuit connection for performing erasure and writing of data in flash memory 3 are different in operation modes (generally referred to as xe2x80x9cnormal mode xe2x80x9d here) other than the flash memory overwriting mode.
Therefore, in the flash memory overwriting mode, operation is controlled such that an overwrite control program is transferred in advance from flash memory 3 to RAM 4, and CPU 1 reads and executes the overwrite control program from RAM 4.
Referring to FIG. 3, the controlling structure of the program executed by the CPU in the flash memory overwriting mode is as follows. When activated, the process transfers the flash memory overwrite control program which has been stored in flash memory 3 to RAM 4 (step S110; hereinafter, xe2x80x9cstepxe2x80x9d is not repeated). Thereafter, control jumps to that area of the RAM to which the flash memory overwrite control program has been transferred (S112). In order to successively read and execute the program on RAM 4, the overwriting mode of the flash memory is set (S114) and in S116, the flash memory is overwritten. When overwriting of the flash memory ends, the overwriting mode of the flash memory is terminated (S118).
In this manner, the contents of the flash memory are overwritten in the overwriting mode of the flash memory.
As can be seen from FIG. 1, the microcomputer includes an interrupt controlling circuit 14. When there is an interrupt request from the peripheral device 13 such a timer or a serial I/O or from a terminal input, not shown, interrupt controlling circuit 14 interrupts execution of the process program by CPU 1 and executes an interruption process. In the interruption process, CPU 1 jumps to that address which is designated by a value stored in an address referred to as xe2x80x9cinterrupt vectorxe2x80x9d existing in flash memory 3, and executes a program at that address, so that a process corresponding to the cause of interruption takes place.
More specifically, when there is an interruption, interrupt controlling circuit 14 automatically outputs an address of the interrupt vector to address bus 8. CPU 1 receives this address, and reads an area designated by the address in flash memory 3, that is, the value of the interrupt vector. Then, CPU 1 jumps to the address designated by the value. The above described series of processes are performed.
The interrupt vector area is generally in flash memory 3 from the following reason. Generally, information which must be held permanently such as the program and the interrupt vector is stored in flash memory 3. If the interrupt vector area were placed in RAM 4, it would become necessary to transfer the data of the interrupt vector to RAM 4 from flash memory 3 immediately after every activation of the microcomputer, as RAM 4 is volatile. In that case, however, interruption is not available if there is an interruption request in a period after reset termination until completion of data transfer of the interrupt vector to the RAM. Therefore, the interrupt vector is generally placed in flash memory 3.
These results in the following problem in the flash memory overwriting mode. Assume that an interruption request is issued while a process in the flash memory overwriting mode described above is being performed by executing the program stored in RAM 4. Here, CPU 1 always tries to read the interrupt vector of flash memory 3. Flash memory 3, however, is being overwritten, and therefore the result of such reading cannot be guaranteed.
In order to avoid such a problem, an interruption is inhibited while the flash memory is being overwritten, by the specification of the microcomputer. More specifically, when such an interruption occurs, the operation is not guaranteed, or alternatively, a mechanism is provided to prevent occurrence of an interruption, by hardware, in the flash memory overwriting mode.
As described above, in a microcomputer including a flash memory of the prior art, interruption is not available while the flash memory is under the overwriting operation. In recent equipments using microcomputers, a process referred to as background operation (BGO) is frequently performed. The BGO function refers to overwriting of data in a certain block within a flash memory while performing normal processing. The function is necessary for overwriting telephone books of cellular phones, overwriting of operational modes, channels, set temperature and other ambient conditions of home use and civil equipments, for example. If the interruption process is not available as in the microcomputer including a flash memory of the prior art, such BGO function cannot be attained.
A possible approach for this problem may be to include two independent flash memories. This approach is impractical as the necessary layout area is too large. An EEPROM (Electrically Erasable ROM) may be included in the microcomputer. The EEPROM, however, is manufactured through a process different from that of the flash memory, and as a result, the overall manufacturing steps of the microcomputer increases, resulting in increased manufacturing cost. Therefore, this approach is impractical.
Another approach is disclosed in Japanese Patent Laying-Open No. 8-185354. In a memory management unit described in this laid-open application, contents of a non-volatile memory are transferred to a random access memory (RAM) when the contents of the non-volatile memory are to be overwritten, and an address of the RAM is exchanged with the address of the non-volatile memory. In this manner, when an interruption occurs while the non-volatile memory is being overwritten, not the non-volatile memory but the RAM is accessed to read the interrupt vector. Thus, a correct interrupt handler can be called.
The technique disclosed in Japanese Patent Laying-Open No. 8-185354, however, still has a problem that even when the interrupt handler is correctly called, subsequent interruption cannot correctly be processed. When the interrupt handler processes an interruption, generally, the RAM is used for saving a stack and for holding operation data. In this case, however, the addresses of the non-volatile memory and the RAM have been exchanged, and therefore, if the interrupt handler were to operate in the normal manner, the non-volatile memory would be used for holding such data. Such an operation, however, is not available generally. Considering such a situation, it may be possible to prepare the interrupt handler such that it always accesses RAM. Preparation of a program in which addresses to be accessed are changed dependent on the situation require formidable time and labor, and hence such an approach is impractical. The necessary cost increases while program reliability may be impaired.
Therefore, an object of the present invention is to implement the BGO function while suppressing increase in cost, in a microcomputer including a flash memory.
Another object of the present invention is to implement the BGO function with high reliability while suppressing increase in cost, in a microcomputer including a flash memory.
The microcomputer including a flash memory in accordance with the present invention includes: a central processing unit; a plurality of storage devices coupled to the central processing unit including a flash memory and address-designated by the central processing unit independently from each other; and an address predecoder connected to receive an address signal from the central processing unit, switching memory mapping between a first memory mapping and a second memory mapping in accordance with memory mapping designating information designating the first memory mapping and the second memory mapping in which at least an address of a prescribed area of the plurality of storage devices different from the flash memory is remapped to a specific area of said flash memory, for the plurality of storage devices, and controlling an access enable mode to the specific area of the flash memory and to the prescribed area of the plurality of storage devices.
The first memory mapping and the second memory mapping are switched in accordance with the memory mapping designating information. As addresses of the prescribed area of the plurality of the storage devices different from the flash memory are remapped to a specific area of the flash memory, the prescribed area is accessed when there is an access to an address of the flash memory while the flash memory is being overwritten. Therefore, even when the flash memory is being overwritten, processing such as an interruption can be handled. Further, as the access enable mode for the prescribed area of the plurality of storage devices and the specific area of the flash memory at this time is controlled by the address predecoder, there is no contradiction even when there is an access directly designating an address of the prescribed area.
Preferably, the address predecoder includes: a storing unit storing the memory mapping designating information; a predecoder for an upper address, connected to upper bits of an address signal from the central processing unit, decoding the upper bits of the address signal and outputting respective selecting signals to the plurality of storage devices, the prescribed area of the plurality of storage devices and specific area of the flash memory; and a logic circuit connected to receive the selection signal output from the predecoder for the upper address and to receive the memory mapping designating information, and adapted to enable replacement of the selection signal for the prescribed area with the selection signal for the specific area, in accordance with a value of the memory mapping designating information.
When the selection signal for the specific area of the flash memory is generated, the selection signal for the prescribed area of another storage device is replaced by the generated signal. As a result, when there is an access to the specific area of the flash memory, actually, an access is made to the prescribed area of another storage device.
According to another aspect of the present invention, the method of operating a microcomputer including a flash memory includes the steps of: transferring data of a first specific area of the flash memory to a first prescribed area of another storage device; remapping the addresses of the first prescribed area to the first specific area; transferring data of a second specific area of the flash memory to a second prescribed area of another storage device as needed; and after transfer of the data of the second specific area, remapping the addresses of the second prescribed area to the second specific area.
Among the data of the flash memory, only those necessary are copied to the prescribed area of another storage device and the addresses are remapped, and when copying of further data is necessary, the data is copied to a still another area and the addresses are remapped. When the data of the flash memory are transferred to another storage device and the flash memory is controlled using the transferred data, it is possible to use an area only of an appropriate size of another storage device.
According to a still further aspect of the present invention, the method of operating a microcomputer including a flash memory includes the steps of: transferring data of a first specific area of the flash memory to first and second prescribed areas of another storage device, updating the data transferred to the first and second prescribed areas with different data; and remapping the addresses of the first or the second prescribed area to the first specific area, in accordance with operation condition of the microcomputer including a flash memory.
The addresses of the first or the second prescribed area can be remaped to the first specific area. Therefore, when the data stored in these areas are updated to data allowing optimal operation of the microcomputer including a flash memory under different conditions and remapping the addresses of the first or the second prescribed area by selecting either of these, the flash memory can be controlled such that overwriting of the flash memory is done with a program optimally operating under the selected condition.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.